In recent years, brushless DC (BLDC) motors have been receiving increasing interest, e.g., for automotive applications. This is due to the higher reliability/longevity, lower maintenance, and quieter operation that a BLDC may have in comparison with its “brushed” DC counterpart. Over the last decade, continuing improvements in power semiconductors and controller ICs as well as the production of permanent-magnet brushless motors have made it possible to manufacture reliable, cost-effective solutions for a broad range of adjustable speed applications.
Applications for which BLDC motors are being designed or currently used include, e.g., power steering, engine cooling fans, fuel/water pumps, air-conditioning compressors, heating, ventilating, and air-conditioning (HVAC) blower motors.
The “phases” of a BLDC motor may be fed with currents subjected to pulse width modulation (PWM) with a variable duty cycle. Control of a BLDC motor may involve sensing the back electro-motive force (Back-EMF), which may occur both during PWM on-time and during PWM off-time.
Back-EMF zero-cross detection during PWM-on time may be critical.
A notionally correct comparison threshold for that purpose is half the DC bus voltage VDC/2 for each motor phase. Certain factors such as, e.g., the variable attenuation introduced by low-pass filtering according to motor speed and the use of low precision resistors for voltage dividers in low-cost application, may result in a correct comparison threshold which is different from the theoretical value and which may be different for each motor phase.
The use of a wrong comparison threshold may result in timing errors for inverter three-phase commutation. These timing errors may produce various drawbacks such as, e.g., an increase of power consumption at a fixed motor speed, an increase of audible noise, and an increase of speed ripple.
For that reason, Back-EMF sensing during PWM off-time may be preferred. However, Back-EMF sensing during PWM off-time requires that a minimum PWM “off” time should be present, so that the PWM duty cycle is constrained to less than 100%. In various applications, this may represent an unacceptable drawback.